As kinds of a non-volatile memory called EEPROM (electrically erasable programmable random memory), there are generally two kinds that are differentiated by quantities of gates. Namely, they are a one-layer gate type and a two-layer gate type. As for the one-layer gate type, technology has been available, such as presented by Japan Provisional Publications No. 6-85275 and No. 8-506693. As for the two-layer gate type, technology has been available, such as presented by Japanese Patent Publication No. 4-80544.
A plan view of a one-layer gate type non-volatile memory is shown in FIG. 28, as a conventional example.
On a P type semiconductor substrate (P substrate) 101, N type diffusion layers 103,105,107 and a control gate 109 consisting of an N type diffusion layer are formed. The N type diffusion layers 103 and 105 are formed with an interval, and the N type diffusion layers 105 and 107 are formed with an interval.
On the P substrate 101 that contains the interval between the N type diffusion layers 103 and 105, a selection gate 111 consisting of a poly silicon film is formed through a gate oxide film (illustration is omitted), partly overlapping with the N type diffusion layers 103 and 105.
A floating gate 113 consisting of a poly silicon film is formed through a silicon oxide film (illustration is omitted) contiguously on the P substrate 101 that includes the interval between the N type diffusion layers 105 and 107, and the control gate 109. Near the interval between the N type diffusion layers 105 and 107, the floating gate 113 is arranged such that it overlaps with the N type diffusion layers 105 and 107 in part through a gate oxide film for the memory.
When erasing the one-layer gate type non-volatile memory, i.e., injecting an electron to the floating gate 113, the N type diffusion layer 107 is set at 0V (volt), and the N type diffusion layer 103 is set at a predetermined potential Vpp, and the predetermined potential Vpp is applied to the control gate 109 and the selection gate 111. In this manner, a transistor is constituted by the N type diffusion layers 103 and 105, and the selection gate 111 is turned on, and the electron is injected into the floating gate 113 through the gate oxide film for the memory from the N type diffusion layer 105.
When writing to the one-layer gate type non-volatile memory, i.e., discharging an electron from the floating gate 113, the control gate 109 is set at 0V, and the N type diffusion layer 107 is opened, and the predetermined potential Vpp is applied to the N type diffusion layer 103 and the selection gate 111. In this manner, the transistor constituted by the N type diffusion layers 103 and 105, and the selection gate 111 is turned on, and the electron injected into the floating gate 113 is drawn out by the N type diffusion layer 103 through the gate oxide film for the memory by the tunnel effect.
In the one-layer gate type non-volatile memory, the control gate 109 formed by the diffusion layer, and the floating gate 113 consisting of the poly silicon film can be overlapped with each other on a large area of the substrate, providing a large coupling ratio.
A sectional view of a two-layer gate type non-volatile memory is shown in FIG. 29, as a conventional example. An N type diffusion layer 117 and an N type diffusion layer 119 are formed on the P substrate 101 with an interval. On the P substrate 101, and between the N type diffusion layers 117 and 119, a floating gate 123, which consists of a poly silicon film, is formed through a gate oxide film 121 for the memory, overlapping in part with the N type diffusion layers 117 and 119. On the floating gate 123, a control gate 127, which consists of a poly silicon film, is formed through a silicon oxide film 125.
When erasing the two-layer gate type non-volatile memory, i.e., injecting an electron to the floating gate 123, the N type diffusion layer 117 is set at 0V, and N type diffusion layer 119 is set at a predetermined potential Vpp, and the predetermined potential Vpp is applied to the control gate 127, thereby, an electron is injected into the floating gate 123 through the gate oxide film 121 for the memory from the N type diffusion layer 119.
When writing to the two-layer gate type non-volatile memory, i.e., discharging an electron from the floating gate 123, the control gate 127 is set at 0V, and the N type diffusion layer 117 is opened, and the predetermined potential Vpp is applied to the N type diffusion layer 119, thereby, the electron injected into the floating gate 123 is drawn out by the N type diffusion layer 119 through the gate oxide film 121 for the memory by the tunnel effect.
In the one-layer gate type non-volatile memory, since the large coupling ratio is available, memory rewriting requires comparatively low voltage. However, since the N type diffusion layer constitutes the control gate 109, there is a problem that a negative voltage cannot be applied to the control gate 109.
In the two-layer gate type non-volatile memory, while a negative voltage can be applied to the control gate 127, due to the control gate 127 being constituted by the poly silicon film, a comparatively large voltage is required in writing, since the coupling ratio is relatively small, as compared with the one-layer gate type non-volatile memory.
Further, when a non-volatile memory is used, a high-voltage transistor is often prepared additionally in order to rewrite to the memory. In order to prevent destruction of the gate oxide film, due to a high voltage applied, the gate oxide film of the high-voltage transistor is formed thicker than the gate oxide film of the memory, which constitutes the memory unit. An example of a method is explained with reference to FIG. 30.
FIG. 30 is a sectional view showing a process that forms the gate oxide films with two values of film thickness.
(1) A unit separation insulation film 129 and a silicon oxide film 131 are formed on the P substrate 101 surface (refer to sub-section (a)).
(2) A resist pattern 133 is prepared with the ordinary phototype process technology, which covers a high-voltage transistor region, and is open at a low voltage transistor region, and then a silicon oxide film 131 of the low voltage transistor region is selectively removed, using the resist pattern 133 as the mask (refer to sub-section (b)).
(3) After removing the resist pattern 133, a low voltage endurance gate oxide film 135 for the low voltage transistor is formed in the low voltage transistor region on the surface of the P substrate 101 by a heat oxidization process, and simultaneously, the silicon oxide film 131 of the high-voltage transistor region is grown up such that a high voltage endurance gate oxide film 137 is formed for the high-voltage transistor, the film being thicker than the low voltage endurance gate oxide film 135 (refer to sub-section (c)). In this manner, two kinds of gate oxide films with different film thickness values are formed.
(4) A poly silicon film is formed all over the P substrate 101, patterning is performed on the poly silicon film such that a gate electrode 139 is formed on the low voltage endurance gate oxide film 135, and a gate electrode 141 is formed on the high voltage endurance gate oxide film 137 (refer to sub-section (d)).
In the above manufacturing method, the high voltage endurance gate oxide film 137 is formed by applying the heat oxidization process twice (hereinafter, called the twice-oxidized film), and the low voltage gate oxide film 135 is formed by the oxide film formed by applying the heat oxidization process once (hereinafter, called once-oxidized film). The twice-oxidized film tends to have less uniformity in film thickness, and lower reliability than the once-oxidized film.
A so-called tunnel oxide film for writing is often formed additionally, which has a film thickness different from the gate oxide films that are used in the low voltage transistor and the high-voltage transistor. In this case, a total of three types of silicon oxide films, having different film thickness, are formed. Usually, the thickest film is formed by applying the heat oxidization process 3 times (called a 3 times-oxidized film, hereinafter) through the manufacturing method described above. By this method, thickness of the 3 times-oxidized film becomes even less uniform than the twice-oxidized film, making it difficult to control total film thickness, and causing reliability to deteriorate.
Since the tunnel oxide film of which reliability is required to be the highest becomes a twice-oxidized film in an advanced miniature process where tunnel oxide film thickness is thicker than gate oxide film thickness of a low voltage transistor, it is feared that reliability may fall, which results from a resist pattern being formed on a silicon oxide film that constitutes a part of the twice-oxidized film in the formation process of the twice-oxidized film.
Further, when the tunnel oxide film thickness and the gate oxide film thickness of the low voltage transistor are close, film thickness control is a highly difficult matter in view of the presence of a natural oxide film that grows up on the semiconductor substrate surface, and controllability of the oxidization furnace used in a heat oxidization process, etc.